`timescale 1ns / 1ps module dcmtest(CLK_50M, LED); input CLK_50M; output [7:0] LED; // 以下のパラメータについてはXAPP462参照。 defparam dcm0.DLL_FREQUENCY_MODE = "LOW"; defparam dcm0.DUTY_CYCLE_CORRECTION = "TRUE"; defparam dcm0.STARTUP_WAIT = "FALSE"; defparam dcm0.CLKDV_DIVIDE = 2.0; defparam dcm0.CLKFX_DIVIDE = 1; defparam dcm0.CLKFX_MULTIPLY = 4; // input wire dcm_clkin; wire dcm_clkfb; reg dcm_dssen; reg dcm_psincdec; reg dcm_psen; reg dcm_psclk; reg dcm_rst; wire dcm_dssen_in; wire dcm_psincdec_in; wire dcm_psen_in; wire dcm_psclk_in; wire dcm_rst_in; assign dcm_dssen_in = dcm_dssen; assign dcm_psincdec_in = dcm_psincdec; assign dcm_psen_in = dcm_psen; assign dcm_psclk_in = dcm_psclk; // assign dcm_dssen_in = 1'b0; // assign dcm_psincdec_in = 1'b0; // assign dcm_psen_in = 1'b0; // assign dcm_psclk_in = 1'b0; assign dcm_rst_in = dcm_rst; // output wire dcm_clk0; wire dcm_clk90; wire dcm_clk180; wire dcm_clk270; wire dcm_clk2x; wire dcm_clk2x180; wire dcm_clkdv; wire dcm_clkfx; wire dcm_clkfx180; wire dcm_locked; wire dcm_psdone; wire [7:0] dcm_status; wire clk; assign dcm_clkin = clk; // reg clk_delay; // IBUFG,BUFG利用(XAPP331参照) IBUFG U_IBUFG0 ( .I(CLK_50M), .O(clk) ); //IBUFG U_IBUFG1 ( BUFG U_IBUFG1 ( // .I(CLK_50M), // .I(clk), .I(dcm_clk0), // .I(clk_delay), .O(dcm_clkfb) ); //always @(clk) //begin // clk_delay <= clk; //end // Spartan-3AではDCMSPを利用する。(XAPP331参照) //DCM dcm0 DCM_SP dcm0 ( .CLKIN (dcm_clkin), .CLKFB (dcm_clkfb), // .CLKFB (dcm_clkin), .DSSEN (dcm_dssen_in), .PSINCDEC (dcm_psincdec_in), .PSEN (dcm_psen_in), .PSCLK (dcm_psclk_in), .RST (dcm_rst_in), .CLK0 (dcm_clk0), .CLK90 (dcm_clk90), .CLK180 (dcm_clk180), .CLK270 (dcm_clk270), .CLK2X (dcm_clk2x), .CLK2X180 (dcm_clk2x180), .CLKDV (dcm_clkdv), .CLKFX (dcm_clkfx), .CLKFX180 (dcm_clkfx180), .LOCKED (dcm_locked), .PSDONE (dcm_psdone), .STATUS (dcm_status) ); reg [31:0] clk90_count; reg [31:0] clk2x_count; reg [31:0] clkdv_count; reg [31:0] clkfx_count; reg clk90; reg clk2x; reg clkdv; reg clkfx; always @(posedge dcm_clk90) begin if (dcm_locked) begin if (clk90_count < 50000000) clk90_count <= clk90_count + 1; else begin clk90_count <= 0; clk90 <= ~clk90; end end end always @(posedge dcm_clk2x) begin if (dcm_locked) begin if (clk2x_count < 50000000) clk2x_count <= clk2x_count + 1; else begin clk2x_count <= 0; clk2x <= ~clk2x; end end end always @(posedge dcm_clkdv) begin if (dcm_locked) begin if (clkdv_count < 50000000) clkdv_count <= clkdv_count + 1; else begin clkdv_count <= 0; clkdv <= ~clkdv; end end end always @(posedge dcm_clkfx) begin if (dcm_locked) begin if (clkfx_count < 50000000) clkfx_count <= clkfx_count + 1; else begin clkfx_count <= 0; clkfx <= ~clkfx; end end end reg start; reg start2; reg [7:0] status; reg [31:0] wait_count; parameter DCM_STATUS_RESET = 1; parameter DCM_STATUS_WAITLOCK = 2; parameter DCM_STATUS_LOCKED = 3; assign LED[0] = clk90; assign LED[1] = clk2x; assign LED[2] = clkdv; assign LED[3] = clkfx; // assign LED[3:1] = dcm_status[2:0]; // assign LED[6:4] = dcm_status[2:0]; assign LED[5:4] = status[1:0]; assign LED[6] = dcm_locked; // assign LED[7] = dcm_rst_in; assign LED[7] = clk; always @(posedge clk) begin if (start == start2) begin start <= ~start; dcm_dssen <= 1'b0; dcm_psincdec <= 1'b0; dcm_psen <= 1'b0; dcm_psclk <= 1'b0; dcm_rst <= 1'b1; //2ns以上(XAPP462参照) status <= DCM_STATUS_RESET; wait_count <= 1; // wait_count <= 100; // wait_count <= 50000000; end else if (wait_count > 0) begin wait_count <= wait_count - 1; end else begin case (status) DCM_STATUS_RESET: begin dcm_rst <= 1'b0; status <= DCM_STATUS_WAITLOCK; end DCM_STATUS_WAITLOCK: begin if (dcm_locked) begin status <= DCM_STATUS_LOCKED; end end DCM_STATUS_LOCKED: begin end default: begin end endcase end end endmodule