`timescale 1ns / 1ps module lcd(CLK_50M, LCD_E, LCD_RS, LCD_RW, LCD_DB, LED, BTN_SOUTH); input CLK_50M; output LCD_E; output LCD_RS; output LCD_RW; output [7:0] LCD_DB; output [7:0] LED; input BTN_SOUTH; reg lcd_e_out; reg lcd_rs_out; reg lcd_rw_out; reg [7:0] lcd_db_out; assign LCD_E = lcd_e_out; assign LCD_RS = lcd_rs_out; assign LCD_RW = lcd_rw_out; assign LCD_DB = lcd_db_out; reg [7:0] state; reg [31:0] clock_count; assign LED[7:0] = state[7:0]; always @(posedge BTN_SOUTH or posedge CLK_50M) begin if (BTN_SOUTH == 1'b1) begin state <= 0; clock_count <= 0; end else begin case (state) // initialize 8'd0 : begin lcd_e_out <= 1'b0; lcd_rs_out <= 1'b0; lcd_rw_out <= 1'b0; lcd_db_out[7:4] <= 4'b0000; lcd_db_out[3:0] <= 4'b1111; clock_count <= 0; state <= state + 1; end 8'd1 : begin if (clock_count < 750000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd2 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'b0011; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd3 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'b0000; lcd_e_out <= 1'b0; end if (clock_count < 205000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd4 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'b0011; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd5 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'b0000; lcd_e_out <= 1'b0; end if (clock_count < 5000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd6 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'b0011; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd7 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'b0000; lcd_e_out <= 1'b0; end if (clock_count < 2000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd8 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'b0010; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd9 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'b0000; lcd_e_out <= 1'b0; end if (clock_count < 2000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end // set parameters // Function Set (0x28) 8'd10 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h2; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd11 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 50) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd12 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h8; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd13 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 2000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end // Entry Mode Set (0x06) 8'd14 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd15 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 50) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd16 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h6; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd17 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 2000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end // Display On/Off (0x0c) 8'd18 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd19 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 50) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd20 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'hc; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd21 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 2000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end // Clear Display (0x01) 8'd22 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd23 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 50) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd24 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h1; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd25 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 82000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end // write letters // Set DD RAM Address (0x80) 8'd26 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h8; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd27 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 50) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd28 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd29 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_e_out <= 1'b0; end if (clock_count < 2000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end // Write Data to CG RAM or DD RAM ('A':0x41) 8'd30 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h4; lcd_rs_out <= 1'b1; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd31 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_rs_out <= 1'b0; lcd_e_out <= 1'b0; end if (clock_count < 50) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd32 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h1; lcd_rs_out <= 1'b1; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd33 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_rs_out <= 1'b0; lcd_e_out <= 1'b0; end if (clock_count < 50000000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd34 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h4; lcd_rs_out <= 1'b1; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd35 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_rs_out <= 1'b0; lcd_e_out <= 1'b0; end if (clock_count < 50) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd36 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h2; lcd_rs_out <= 1'b1; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd37 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_rs_out <= 1'b0; lcd_e_out <= 1'b0; end if (clock_count < 50000000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd38 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h4; lcd_rs_out <= 1'b1; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd39 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_rs_out <= 1'b0; lcd_e_out <= 1'b0; end if (clock_count < 50) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd40 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h3; lcd_rs_out <= 1'b1; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd41 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_rs_out <= 1'b0; lcd_e_out <= 1'b0; end if (clock_count < 50000000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd42 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h4; lcd_rs_out <= 1'b1; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd43 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_rs_out <= 1'b0; lcd_e_out <= 1'b0; end if (clock_count < 50) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd44 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h4; lcd_rs_out <= 1'b1; end if (clock_count == 2) begin lcd_e_out <= 1'b1; end if (clock_count < 14) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end 8'd45 : begin if (clock_count == 0) begin lcd_db_out[7:4] <= 4'h0; lcd_rs_out <= 1'b0; lcd_e_out <= 1'b0; end if (clock_count < 50000000) begin clock_count <= clock_count + 1; end else begin clock_count <= 0; state <= state + 1; end end default : begin clock_count <= clock_count + 1; end endcase end end endmodule